Decoding circuit and reproduction apparatus which mutes audio after header parameter changes

ABSTRACT

A decoding circuit, for receiving a bit stream including an encoded audio signal and header information used for-decoding the encoded audio signal, and decoding the encoded audio signal based on the header information, includes a header analysis section for outputting at least one decoding parameter obtained from the header information and decoding parameter change information indicating whether or not the at least one decoding parameter has been changed; a signal processing section for decoding the encoded audio signal, based on the at least one decoding parameter, into a decoded signal and outputting the decoded signal; an automatic mute processing section for executing automatic mute on the decoded signal after the at least one decoding parameter is changed; and an output section for outputting the decoded signal output from the automatic mute processing section.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a decoding circuit for decoding an encoded bit stream produced from an audio signal and a reproduction apparatus including the same.

2. Description of hte Related Art

An encoded bit stream produced in an audio signal encoding system generally includes an encoded audio signal and header information, which is decoding information used for decoding the encoded audio signal. The header information includes decoding parameters such as, for example, sampling frequency information, emphasis information, number of channels, and channel mode information. Such an encoded bit stream is produced by, for example, MPEG1 and MPEG2 audio signal encoding systems (see, ISO/IEC 11172-3:1993 and ISO/IEC CD 13818-3.2).

A reproduction apparatus for reproducing such an encoded bit stream generally includes a decoding circuit for decoding the encoded bit stream and thus generating a digital output signal, a D/A converter for converting the digital output signal into an analog signal, peripheral circuits such as, for example, a medium data extraction circuit for transferring the encoded bit stream from the medium storing the encoded bit stream to the decoding circuit, and a CPU for performing overall control of the reproduction apparatus.

FIG. 5 is a block diagram illustrating a structure of a reproduction apparatus 500 for reproducing an MPEG1 encoded audio signal. The reproduction apparatus 500 operates in the following manner.

An MPEG1 audio bit stream extracted from a medium data extraction circuit 531 is sent to a stream buffer 532 by the control of a CPU 533. Upon an instruction from the CPU 533, a decoding circuit 534 starts decoding the audio bit stream. The decoding circuit 534 operates in the following manner.

The audio bit stream is read by a stream reading section 342. A header analysis section 343 extracts header information from the audio bit stream and performs header analysis, thereby obtaining decoding parameters such as, for example, sampling frequency information, layer information and channel mode information.

The sampling frequency information obtained by the header analysis section 343 is sent to the CPU 533 through a host interface section 341, and the CPU 533 sets a D/A converter 536.

The decoding circuit 534, after header analysis, decodes the encoded audio signal by a signal processing section 344, based on the decoding parameters obtained by the header analysis section 343, into a digital output signal. The resultant digital output signal is sent to an output buffer 535 by an output section 345. The digital output signal temporarily stored in the output buffer 535 is sequentially read and converted into an analog signal by the D/A converter 536, which is output outside.

The reproduction apparatus 500 has the following problems.

(1) When the sampling frequency is changed during reproduction, the sampling frequency for the D/A converter 536. needs to be reset. However, it is very difficult to reset the sampling frequency in synchronization with the decoding processing performed by the decoding circuit 534. The reasons are that resetting of the D/A converter 536 is time-consuming and that there is a delay from the change in the sampling frequency until the CPU 533 is informed of the change in the sampling frequency.

Such a change in the decoding parameters can actually occur as a result of a change in the track or channel of the reproduction stream. In the decoding circuit and reproduction apparatus as described above, an extraneous or discordant sound (noise) is output when such a change in the decoding parameters occurs.

(2) For reproducing an encoded bit stream packetized with time stamp information resulting from the DVD format or STB (set top box) format used, the bit stream needs to be decoded in synchronization with the time stamp information into a digital output signal to be output.

When the encoded bit stream to be decoded is, for example, an MPEG encoded audio stream, the number of output data samples per frame-and the reproduction time vary in accordance with the decoding parameters included in the header information, such as, for example, sampling frequency information, layer information, and ID information indicating whether or not half rate sampling is performed.

When such decoding parameters change during reproduction and the encoded bit stream continues to be decoded in synchronization with the time stamp information without resetting the internal decoding processing, an extraneous or discordant sound is output.

SUMMARY OF THE INVENTION

According to one aspect of the invention, a decoding circuit, for receiving a bit stream including an encoded audio signal and header information used for decoding the encoded audio signal, and decoding the encoded audio signal based on the header information, includes a header analysis section for outputting at least one decoding parameter obtained from the header information and decoding parameter change information indicating whether or not the at least one decoding parameter has been changed; a signal processing section for decoding the encoded audio signal, based on the at least one decoding parameter, into a decoded signal and outputting the decoded signal; an automatic mute processing section for executing automatic mute on the decoded signal after the at least one decoding parameter is changed; and an output section for outputting the decoded signal output from the automatic mute processing section.

In one embodiment of the invention, the automatic mute processing section executes the automatic mute for a prescribed duration of time.

In one embodiment of the invention, the decoding circuit further includes a host interface section for communicating with a control circuit for controlling the decoding circuit.

In one embodiment of the invention, the host interface section includes an automatic mute instruction section which is set to instruct whether or not automatic mute is necessary.

In one embodiment of the invention, the at least one decoding parameter includes sampling frequency information. The decoding parameter change information is sampling frequency change information indicating whether or not the sampling frequency information has been changed. The automatic mute processing section executes the automatic mute based on the sampling frequency change information. The automatic mute processing instruction section includes a sampling frequency change automatic mute instruction section which is set to instruct whether or not the automatic mute is necessary based on the change in the sampling frequency information.

In one embodiment of the invention, the at least one decoding parameter includes emphasis information. The decoding parameter change information is emphasis change information indicating whether or not the emphasis information has been changed. The automatic mute processing section executes the automatic mute based on the emphasis change information. The automatic mute processing instruction section includes an emphasis change automatic mute instruction section which is set to instruct whether or not the automatic mute is necessary based on the change in the emphasis information.

In one embodiment of the invention, the at least one decoding parameter includes channel mode information. The decoding parameter change information is channel mode change information indicating whether or not the channel mode information has been changed. The automatic mute processing section executes the automatic mute based on the channel mode change information. The automatic mute processing instruction section includes a channel mode change automatic mute instruction section which is set to instruct whether or not the automatic mute is necessary based on the change in the channel mode information.

In one embodiment of the invention, the bit stream includes an MPEG encoded audio bit stream.

In one embodiment of the invention, the at least one decoding parameter includes layer information. The decoding parameter change information is layer change information indicating whether or not the layer information has been changed. The automatic mute processing section executes the automatic mute based on the layer change information. The automatic mute processing instruction section includes a layer change automatic mute instruction section which is set to instruct whether or not the automatic mute is necessary based on the change in the layer information.

In one embodiment of the invention, the at least one decoding parameter includes ID information. The decoding parameter change information is ID change information indicating whether or not the ID information has been changed. The automatic mute processing section executes the automatic mute based on the ID change information. The automatic mute processing instruction section includes an ID change automatic mute instruction section which is set to instruct whether or not the automatic mute is necessary based on the change in the ID information.

In one embodiment of the invention, the decoding circuit further includes an initialization section for automatically initializing decoding processing performed by the decoding circuit, wherein the host interface section includes an initialization instruction section for instructing the initialization section to initialize the decoding processing upon receipt of an instruction from the control circuit.

In one embodiment of the invention, the host interface section includes a parameter display section for outputting the at least one decoding parameter to the control circuit, and a parameter change interrupt section for outputting the decoding parameter change information to the control circuit.

In one embodiment of the invention, the host interface section includes an automatic mute timer setting section for setting a time duration. The automatic mute processing section terminates the automatic mute based on an instruction from the automatic mute timer setting section.

In one embodiment of the invention, the host interface section includes an automatic mute release instruction section which is set by the control circuit whether or not to instruct automatic mute release. The automatic mute processing section terminates the automatic mute based on an instruction from the automatic mute release instruction section.

In one embodiment of the invention, the at least one decoding parameter includes sampling frequency information. The decoding parameter change information is sampling frequency change information indicating whether or not the sampling frequency information has been changed. The automatic mute processing section starts the automatic mute based on the sampling frequency change information.

In one embodiment of the invention, the at least one decoding parameter includes emphases information. The decoding parameter change information is emphasis change information indicating whether or not the emphases information has been changed. The automatic mute processing section starts the automatic mute based on the emphasis change information.

In one embodiment of the invention, the at least one decoding parameter includes channel mode information. The decoding parameter change information is channel mode change information indicating whether or not the channel mode information has been changed. The automatic mute processing section starts the automatic mute based on the channel mode change information.

In one embodiment of the invention, the bit stream includes an MPEG encoded audio bit stream.

In one embodiment of the invention, the at least one decoding parameter includes layer information. The decoding parameter change information is layer change information indicating whether or not the layer information has been changed. The automatic mute processing section starts the automatic mute based on the layer change information.

In one embodiment of the invention, the decoding parameter includes ID information. The decoding parameter change information is ID change information indicating whether or not the ID information has been changed. The automatic mute processing section starts the automatic mute based on the ID change information.

According to another aspect of the invention, a reproduction apparatus includes the above-described decoding circuit, and a control circuit for controlling the decoding circuit.

In one embodiment of the invention, the reproduction apparatus further includes a medium data extraction circuit for extracting an encoded audio signal and header information from an input encoded audio bit stream and outputting the encoded audio signal and the header information to the decoding circuit.

In one embodiment of the invention, the reproduction apparatus further includes a D/A converter for D/A converting a decoded signal output from the decoding circuit.

In one embodiment of the invention, the control circuit stops an operation of the medium data extraction circuit based on decoding parameter change information obtained from the header information.

In one embodiment of the invention, the control circuit sets a sampling frequency for the D/A converter based on the decoding parameter change information obtained from the header information.

In one embodiment of the invention, the control circuit resets the decoding circuit based on the decoding parameter change information obtained from the header information.

In one embodiment of the invention, the control circuit restarts an operation of the medium data extraction circuit based on the decoding parameter change information obtained from the header information.

Thus, the invention described herein makes possible the advantages of providing a decoding circuit for decoding an encoded bit stream without outputting an extraneous or discordant sound even when a decoding parameter changes during reproduction, and a reproduction apparatus including such a decoding circuit.

These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a basic structure of a reproduction apparatus in an example according to the present invention;

FIG. 2 is a diagram illustrating a structure of a host interface section shown in FIG. 1;

FIGS. 3 and 4 are flowcharts illustrating an exemplary operation of the reproduction apparatus shown in FIG. 1; and

FIG. 5 is a block diagram illustrating a structure of a conventional reproduction apparatus.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the present invention will be described by way of illustrative examples with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a basic structure of a reproduction apparatus 100 in an example according to the present invention. For simplicity, the reproduction apparatus 100 extracts and reproduces an MPEG encoded audio bit stream (hereinafter, also referred to simply as, “encoded bit stream”) from a broadcasting radio wave such as STB or the like or a specific medium such as a DVD or the like.

The encoded bit stream includes an encoded audio signal and header information. The header information includes decoding parameters. The decoding parameters include sampling frequency information, emphasis information, channel mode information, layer information, and ID information.

Herein, it is assumed that during the reproduction of a bit stream, the sampling frequency information is first changed and then the layer information is changed.

In the case of an MPEG encoded bit stream based on an audio signal, the sampling frequency indicated by the header information is as follows. When ID bit=1, the sampling frequency is either 44.1 kHz, 48 kHz, or 32 kHz. When ID bit=0, the sampling frequency is either 22.05 kHz, 24 kHz, or 16 kHz.

The number of output data samples per frame varies in accordance with the layer information indicated by the header information. For example, the number of output data samples is 348 samples per frame in layer 1, and 1152 samples in layer 2.

As shown in FIG. 1, the reproduction apparatus 100 includes a medium-data extraction circuit 11, a stream buffer 12, a CPU 13, a decoding circuit 14, an output buffer 15, and a D/A converter 16.

The decoding circuit 14 includes a stream reading section 143, a header analysis section 144, a signal processing section 145, an automatic mute processing section 146, an output section 147, a host interface section 141, and an initialization section 142.

As shown in FIGS. 1 and 2, the host interface section 141 includes an initialization instruction section 21, a parameter display section 22, a parameter change interrupt section 23, an automatic mute instruction section 24, an automatic mute timer setting section 25, and an automatic mute release instruction section 26.

As shown in FIG. 2, the automatic mute instruction section 24 includes a sampling frequency change automatic mute instruction section 241, an ID change automatic mute instruction section 242, a layer change automatic mute instruction section 243, an emphasis change automatic mute instruction section 244, and a channel mode change automatic mute instruction section 245.

Returning to FIG. 1, the elements of the reproduction apparatus 100 operate in, for example, the following manner.

The medium data extraction circuit 11 extracts an encoded bit stream 32 from a broadcasting radio wave such as STB or the like, or a specific medium such as a DVD or the like, and then sends the encoded bit stream 32 to the stream buffer 12. The encoded bit stream 32 includes an encoded audio signal and header information.

The CPU 13 controls data input to and output from the reproduction apparatus 100, decoding performed by the decoding circuit 14, and other operations of the reproduction apparatus 100. Based on an instruction from the CPU 13, the decoding circuit 14 decodes the encoded audio signal sent from the stream buffer 12, and outputs a resultant digital output signal 37 to the output buffer 15.

The D/A converter 16 reads the digital output signal 37 from the output buffer 15 based on the sampling frequency information set by the CPU 13 and converts the digital output signal 37 into an analog signal 34, which is output outside.

The elements of the decoding circuit 14 operate in, for example, the following manner.

The host interface section 141 communicates with the CPU 13. The initialization section 142, upon receipt of a reset instruction from the CPU 13 through the host interface section 141, resets the stream reading section 143, the header analysis section 144, the signal processing .section 145, the automatic mute processing section 146, and the output section 147.

The stream reading section 143 reads the encoded bit stream 32 from the stream buffer 12.

The header analysis section 144 extracts the header information from the encoded bit stream 32, analyzes the header information, and obtains decoding parameters 35 from the header information. The decoding parameters 35 are sent to the parameter display section 22. When any of the decoding parameters 35 are changed, the header analysis section 144 sends interrupt information 36 (decoding parameter change information) regarding the changed decoding parameter to the parameter change interrupt section 23.

The signal processing section 145 decodes the encoded audio signal based on the decoding parameters 35 obtained by the header analysis section 144 and thus generates the digital output signal 37.

The automatic mute processing section 146 executes automatic mute of the digital output signal 37 after the change in the decoding parameters, based on an automatic mute instruction from the automatic mute instruction section 24.

The output section 147 receives the digital output signal 37 from the automatic mute processing section.146 and outputs the digital output signal 37 to the output buffer 15.

The initialization instruction section 21, upon receipt of a reset instruction from the CPU 13, instructs the initialization section 142 to reset the decoding circuit 14. The parameter display section 22 sends the parameters 35 obtained by the header analysis section 144 to the CPU 13. When there has been a change in any of the decoding parameters 35 extracted by the header analysis section 144, the parameter change interrupt section 23 sends the interrupt information 36 to the CPU 13, thereby informing the CPU 13 of the change in the decoding parameters 35. The interrupt information 36 is processed with priority over the other processing of the CPU 13.

The CPU 13 sets the automatic mute instruction section 24 to instruct automatic mute regarding various changes in the decoding parameters 35. The CPU 13 sets an automatic mute time duration in the automatic mute timer setting section 25. The automatic mute timer setting section 25 having the automatic mute time duration set therein instructs the automatic mute processing section 146 to release the automatic mute when the set time duration elapses after the start of the mute.

The CPU 13 sets an automatic mute release in the automatic mute release instruction section 26. When the automatic mute release is set by the CPU 13, the automatic mute release instruction section 26 instructs the automatic mute processing section 146 to release the automatic mute.

Only one of the automatic mute timer setting section 25 and the automatic mute release instruction section 26 need be provided.

The CPU 13 presets in the sampling frequency change automatic mute instruction section 241 whether automatic mute is required or not after the sampling frequency information is changed. The CPU 13 presets in the ID change automatic mute instruction section 242 whether automatic mute is required or not after the ID information is changed. The CPU 13 presets in the layer change automatic mute instruction section 243 whether automatic mute is required or not after the layer information is changed. The CPU 13 presets in the emphasis change automatic mute instruction section 244 whether automatic mute is required or not after the emphasis information is changed. The CPU 13 presets in the channel mode change automatic mute instruction section 245 whether automatic mute is required or not after the channel mode information is changed.

An exemplary operation of the reproduction apparatus 100 having the above-described structure will be described with reference to flowcharts in FIGS. 3 and 4.

The initialization section 142, upon receipt of a reset instruction from the CPU 13 through the host interface section 141, resets the stream reading section 143, the header analysis section 144, the signal processing section 145, the automatic mute processing section 146, and the output section 147 (step S1).

The CPU 13 sets the sampling frequency change automatic mute instruction section 241 to instruct automatic mute after the sampling frequency information is changed (step S2). It is assumed that the CPU 13 has not set the ID change automatic mute instruction section 242, the layer change automatic mute instruction section 243, the emphasis change automatic mute instruction section 244, or the channel mode change automatic mute instruction section 245 to instruct automatic mute when the respective decoding parameter is changed.

The medium data extraction circuit 11, based on an instruction from the CPU 13, outputs the encoded bit stream 32 to the stream buffer 12 (step S3). The decoding circuit 14 decodes the encoded bit stream 32 sent from the stream buffer 12 as follows.

The stream reading section 143 reads the encoded bit stream 32 from the stream buffer 12 (step S4). The header analysis section 144 extracts header information from the encoded bit stream 32 and performs header analysis, thereby obtaining the decoding parameters 35 (step S5). The header analysis section 144 also determines whether or not there has been a change in each of the decoding parameters 35 (step S6).

When it is determined that there has been a change in the decoding parameters 35, the header analysis section 144 sends the parameter change interrupt information 36 to the parameter change interrupt section 23. The header analysis section 144 also sends the decoding parameters 35 to the parameter display section 22 (step S7). The parameter change interrupt section 23 sends the parameter change interrupt information 36 to the CPU 13. The parameter change interrupt information 36 is processed with priority over the other processing of the CPU 13. The parameter display section 22 sends the decoding parameters 35 to the CPU 13 (step S8).

Then, it is determined whether or not the automatic mute processing section 146 is executing automatic mute (step S9). When it is determined that the automatic mute processing section 146 is executing the automatic mute (“yes” in step S9), it is determined whether or not automatic mute release is set in the automatic mute release instruction section 26 (step S10).

When it is determined that the automatic mute release is not set in the automatic mute release instruction section 26 (“no” in step S10), it is determined whether or not an automatic mute time duration is set in the automatic mute timer setting section 25 (step S11).

When it is determined that the automatic mute time duration is set in the automatic mute timer setting section 25 (“yes” in step S11), it is determined whether or not the time duration in which the automatic mute processing section 146 has been executing automatic mute is shorter than the automatic mute time duration which is set in the automatic mute timer setting section 25 (step S12). When it is determined that the time duration in which the automatic mute processing section 146 has been executing the automatic mute is not shorter than the automatic mute time duration which is set in the automatic mute timer setting section 25 (“no” in step S12), the automatic mute timer setting section 25 understands that the set time has elapsed after the start of the mute and instructs the automatic mute processing section 146 to release the automatic mute. The automatic mute processing section 146 then terminates the execution of the automatic mute (step S13).

When it is determined that the automatic mute release is set in the automatic mute release section 26 (“yes” in step S10), the automatic mute release instruction section 26 instructs the automatic mute processing section 146 to release the automatic mute. The automatic mute processing section 146 then terminates the execution of the automatic mute (step S14).

When it is determined that the automatic mute processing section 146 is not executing the automatic mute (“no” in step S9), when it is determined that the automatic mute time duration is not set in the automatic mute timer setting section 25 (“no” in step S11), when it is determined that the time duration in which the automatic mute processing section 146 has been executing the automatic mute is shorter than the automatic mute time duration which is set in the automatic mute timer setting section 25 (“yes” in step S12), or after the automatic mute processing section 146 terminates the execution of the automatic mute by the instruction from the automatic mute timer setting section 25 (step S13) or by the instruction from the automatic mute release instruction section 26 (step S14), the CPU 13 determines whether or not there has been a change in the decoding parameters 35 (step S15).

When it is determined that there has been a change in the decoding parameters 35 (“yes” in step S15), the CPU 13 sends an automatic mute instruction for the changed decoding parameter to the automatic mute instruction section 24 (step, S16).

The automatic mute instruction section 24 determines whether or not the automatic mute for the changed decoding parameter is set (step S17). When it is determined that the automatic mute for the changed decoding parameter is set (“yes” in step S17), the automatic mute instruction section 24 instructs the automatic mute processing section 146 to start automatic mute (step S18).

When it is determined that there has been no change in the decoding parameters 35 (“no” in step S15), when it is determined that the automatic mute for the changed decoding parameter is not set (“no” in step S17), or after the automatic mute instruction section 24 instructs the automatic mute processing section 146 to start automatic mute (step S18), the signal processing section 145 decodes the encoded audio signal based on the decoding parameters 35 obtained by the header analysis section 144 and thus generates the digital output signal 37, which is output (step S19).

Then, it is determined whether or not the automatic mute instruction section 24 has instructed the automatic mute processing section 146 to start automatic mute (step S20). When it is determined that the start of the automatic mute has been instructed (“yes” in step S20), the automatic mute processing section 146 performs automatic mute on the digital output signal 37 (step S21).

When it is determined that the start of the automatic mute has not been instructed (“no” in step S20) or after the automatic mute processing section 146 performs automatic mute on the digital output signal 37 (step S21), the output section 147 receives the digital output signal 37 from the automatic mute processing section 146 and outputs the digital output signal 37 to the output buffer 15 (step S22).

Then, it is determined whether or not the CPU 13 has issued a reset instruction (step S23). When it is determined that the CPU 13 has issued a reset instruction (“yes” in step S23), the processing returns to step S1. When it is determined that the CPU 13 has not issued a reset instruction (“no” in step S23), the processing returns to step S4.

In this example, the determination in step S23 is performed after the output section 147 outputs the digital output signal 37 to the output buffer 15 (step S22). The determination in step S23 can be done at other times.

The reproduction apparatus 100 (FIG. 1) operates in the following manner in the case where no change is made in the decoding parameters 35 and no automatic mute is performed.

In step S19, the signal processing section 145 decodes the encoded audio signal obtained by the header analysis section 144 and thus generates the digital output signal 37.

The automatic mute processing section 146 sends the digital output signal 37 as it is to the output section 147 since the decoding parameters have not been changed and automatic mute has not been instructed (“no” in step S20). The output section 147 sends the digital output signal 37 to the output buffer 15 (step S22).

Then, the digital output signal 37 is read and converted into an analog signal by the D/A converter 16, which is output outside. Unless the CPU 13 issues a reset instruction, the processing returns to step S4 and repeats the frame-by-frame decoding of the encoded bit stream read by the stream reading section 143.

An exemplary operation of the reproduction apparatus 100 when the sampling frequency information changes during the reproduction will be described with reference to FIGS. 1, 3 and 4.

As described above, the decoding of the encoded bit stream 32 is performed on a frame-by-frame basis. The stream reading section 143 reads the encoded bit stream 32 from the stream buffer 12. Then, the header analysis section 144 performs extraction and analysis of the header information and thus obtains the decoding parameters 35 (step S5).

In step S6, the header analysis section 144 compares the decoding parameters 35 just analyzed and the decoding parameters obtained in the preceding frame to recognize that the sampling frequency information has been changed. In step S7, the header analysis section 144 sends the interrupt information 36, indicating a change in the sampling frequency information, to the parameter change interrupt section 23, and also sends the decoding parameters 35 including the sampling frequency information obtained by the header analysis section 144 in the present frame to the parameter display section 22.

In step S8, the parameter change interrupt section 23 sends the interrupt information 36 to the CPU 13, and the parameter display section 22 sends the decoding parameters 35 including the sampling frequency information to the CPU 13.

Unless the automatic mute is being executed in step S9, the processing advances to step S16.

In step S16, the CPU 13 sends an automatic mute instruction for the sampling frequency information to the automatic mute instruction section 24 (step S16).

In step S17, the automatic mute instruction section 24 determines whether or not the automatic mute for the sampling frequency information is set. When the automatic mute for the sampling frequency information is set, the automatic mute instruction section 24 instructs the automatic mute processing section 146 to start automatic mute in step S18.

Then, the signal processing section 145 decodes the encoded audio signal in the encoded bit stream 32 based on the decoding parameters 35 obtained by the header analysis section 144 and thus outputs the digital output signal 37.

Since the automatic mute for the sampling frequency information is set, the start of the automatic mute is instructed in step S18. Accordingly, the digital output signal 37 from the signal processing section 145 is muted by the automatic mute processing section 146 (step S21) and thus is made silent.

Therefore, the silent signal is output from the output section 147 as the digital output signal 37. Then, the silent signal is sent to the output buffer 15 and then converted into an analog signal by the D/A converter 16 to be output outside. This procedure is continued until the CPU 13 issues a reset instruction.

The CPU 13 receives the interrupt information 36, from the parameter change interrupt section 23, indicating that the sampling frequency information has been changed. The CPU 13 also receives the post-change sampling frequency information from the parameter display section 22.

The CPU 13 instructs the medium data extraction circuit 11 to stop receiving the encoded bit stream 32 from the stream buffer 12, and also sets the D/A converter 16 based on the post-change sampling frequency information obtained from the parameter display section 22.

When the setting of the D/A converter 16 is completed, the CPU 13 instructs the decoding circuit 14, through the initialization instruction section 21 of the host interface section 141, to reset the decoding processing, and also instructs the medium data extraction circuit 11 to restart receiving the encoded bit stream 32 from the stream buffer 12.

The decoding circuit 14, upon receipt of the reset instruction, performs in a manner similar to when starting the decoding processing. Namely, the processing returns to step S1, where the internal reset of the decoding circuit 14 is performed by the initialization section 142. Thus, decoding processing is restarted.

Next, an exemplary operation of the reproduction apparatus 100 when the layer information changes during the reproduction will be described with reference to FIGS. 1, 3 and 4.

The CPU 13 has already instructed the sampling frequency change automatic mute instruction section 241 to perform automatic mute when the sampling frequency information is changed. However, no automatic mute instruction has been given regarding a change in the other parameters. The decoding circuit 14 decodes the encoded bit stream 32 on a frame-by-frame basis.

The stream reading section 143 reads the encoded bit stream 32 from the stream buffer 12. Then, the header analysis section 144 performs extraction and analysis of the header information and thus obtains the decoding parameters 35 (step S5).

In step S6, the header analysis section 144 compares the decoding parameters 35 just analyzed and the decoding parameters obtained in the preceding frame to recognize that the layer information has been changed. In step S7, the header analysis section 144 sends the interrupt information 36, indicating a change in the layer information, to the parameter change interrupt section 23, and also sends the decoding parameters 35 including the layer information obtained by the header analysis section 144 in the present frame to the parameter display section 22.

In step S8, the parameter change interrupt section 23 sends the interrupt information 36 to the CPU 13, and the parameter display section 22 sends the decoding parameters 35 including layer information to the CPU 13.

Unless the automatic mute is being executed in step S9, the processing advances to step S16.

In step S16, the CPU 13 sends an automatic mute instruction for the layer information to the automatic mute instruction section 24 (step S16).

Since no automatic mute for the layer information is set in the layer change automatic mute instruction section 243 (“no” in step S17), the automatic mute instruction section 24 does not instruct the automatic mute processing section 146 to start automatic mute.

The signal processing section 145 decodes the encoded audio signal in the encoded bit stream 32 based on the decoding parameters 35 obtained by the header analysis section 144 and thus outputs the digital output signal 37.

The layer information has been changed, but the automatic mute for the layer information has not been set in the layer change automatic mute instruction section 243. Therefore, the layer change automatic mute instruction section 243 does not instruct the automatic mute processing section 146 to start automatic mute. Accordingly, the digital output signal 37 is sent to the output section 147 without being muted by the automatic mute processing section 146.

Then, the digital output signal 37 is sent to the output buffer 15 and converted by the D/A converter 16 into an analog signal to be output outside.

In the above, the operation of the reproduction apparatus 100 when the sampling frequency information is changed and when the layer information is changed is described. The reproduction apparatus 100 operates in a similar manner when the emphasis information, channel mode information or ID information is changed.

In the above example, the decoding circuit 14 performs automatic mute only when the sampling frequency information is changed. The present invention is not limited to such an operation. The decoding circuit 14 according to the present invention can appropriately perform automatic mute when any of the decoding parameters is changed, by simply setting the automatic mute regarding each decoding parameter in a desired manner.

For example, in the case where the automatic mute is set by the CPU 13 in the layer change automatic mute instruction section 243, the layer change automatic mute instruction section 243 instructs the automatic mute processing section 146 to start automatic mute when the layer information is changed. Then, the automatic mute processing section 146 executes automatic mute on the digital output signal 37. The digital output signal 37 processed with automatic mute is sent to the output section 147.

Among the decoding parameters mentioned in the above example, the sampling frequency information, emphasis information, and ID information in the case where the decoding circuit 14 does not have a function of performing up-sampling for half rate reproduction require the D/A converter 16 to be reset when they are changed. The layer information and the channel mode information do not necessarily require the D/A converter 16 to be reset.

In the case where the decoding circuit 14 has a function of performing up-sampling for half-rate reproduction, the D/A converter 16 does not need to be reset when the ID information is changed.

Thus, owing to the automatic mute, the decoding parameters which require the D/A converter 16 to be reset can be changed by the CPU 13, assuredly without outputting an extraneous or discordant sound, by simply performing internal reset of the decoding circuit 14 after the resetting of the D/A converter 16 is completed.

For the decoding parameters which do not require the D/A converter 16 to be reset, e.g., the layer information, the channel mode information, and the ID information in the case where the decoding circuit 14 has a function of performing up-sampling for half rate reproduction, automatic mute does not need to be performed.

In the case where the decoding circuit 14 is conforming to reproduction of bit streams including time stamp, such as a decoding circuit included in a disk reproduction apparatus conforming to almost all DVD formats, the CPU 13 can only reset the D/A converter 16 regarding decoding parameters which require a change in time management data. Regarding the other decoding parameters, the CPU 13 can only release automatic mute by the automatic mute timer setting section 25 or the automatic mute release instruction means 26.

Among the decoding parameters described in the above example, the sampling frequency information, the ID information, and the layer information require a change in the time management data.

For example, in the case where the automatic mute time duration is set in the automatic mute timer setting section 25 in step S11, the time duration in which the automatic mute processing section 146 has been executing automatic mute is compared with the automatic mute time duration which is set in the automatic mute timer setting section 25 in step S12. When the time duration in which the automatic mute processing section 146 has been executing the automatic mute is determined not to have reached the automatic mute time duration set in the automatic mute timer setting section 25, the processing advances to step S15. When the time duration in which the automatic mute processing section 146 has been executing the automatic mute is determined to have reached the automatic mute time duration set in the automatic mute timer setting section 25, the processing advances to step S13, where the automatic mute is released. In this manner, the automatic mute is automatically released after a prescribed duration of time.

In the case where automatic mute release is determined to be set in the automatic mute release instruction section 26 in step S10, the processing advances to step S14, where the automatic mute is released by the automatic mute release instruction section 26.

Although not described above, fade-out processing immediately before the automatic mute or fade-in processing at the restart immediately after the automatic mute can be performed. Needless to say, automatic mute can be more effective with the fade-out or fade-in processing. Notably, the fade-out and fade-in processing needs to be set to be performed after the header analysis of the immediately subsequent frame.

In the above example, automatic mute is released by internal reset of the decoding circuit 14. An appropriate one of the initialization instruction section 21, the automatic mute timer setting section 25, and the automatic mute release instruction section 26, included in the host interface section 141, can be used for mute or reset as required by changes in different decoding parameters. Thus, more effective mute or reset can be performed.

For example, a time duration required for resetting the D/A converter 16 can be set in the automatic mute timer setting section 25. When only the emphasis information is changed, which does not require internal reset of the decoding circuit 14, the automatic mute can be automatically released when the time duration set in the automatic mute timer setting section 25 elapses after the start of automatic mute.

When automatic mute is required only during a transition duration of the delay caused by a band synthesis filter, such as when the channel mode information is changed, automatic mute can be automatically released by the automatic mute release instruction section 26 immediately after the start of the automatic mute is detected.

The decoding circuit 14 in the present invention is usually formed of an LSI or DSP for medium decoding, and thus is often treated as one independent component in a reproduction system. Such a decoding circuit is mostly developed separately from the CPU for performing the overall control of the reproduction system.

In the case where the decoding circuit 14 is designed as an independent LSI, the compatibility with the CPU can be improved by designing the decoding circuit 14 so as to be compatible with various types of devices regarding the automatic mute and reset. Use of such a decoding circuit facilitates designing of reproduction apparatuses.

As described above, the decoding circuit according to the present invention includes an automatic mute processing section for executing automatic mute on a decoded signal after at least one decoding parameter obtained by the header analysis section is changed. Thus, timely mute is allowed to be performed immediately after the change in the decoding parameter.

The decoding circuit according to the present invention includes an automatic mute processing section for executing automatic mute for a prescribed duration of time in accordance with a change in at least one decoding parameter obtained by the header analysis section. Thus, timely mute is allowed to be performed immediately after the change in the decoding parameter.

The decoding circuit according to the present invention includes an automatic mute instruction section which is set to instruct whether or not automatic mute is made necessary by a change in a decoding parameter in a host interface section. Thus, the automatic mute is allowed to be performed only when the decoding parameter designated outside is changed.

The decoding circuit according to the present invention includes an initialization section for automatically initializing the decoding processing. The host interface section of the decoding circuit includes a parameter display section, a parameter change interrupt section, and an initialization instruction section. Thus, the timely start of the automatic mute is realized immediately after the change in a decoding parameter and the decoding circuit is allowed to be initialized after an arbitrary duration of time.

In the case where the automatic mute processing section performs automatic mute based on a change in sampling frequency information obtained by the header analysis section, timely mute is allowed to be performed immediately after the change in the sampling frequency information.

In the case where the automatic mute processing section performs automatic mute based on a change in emphasis information obtained by the header analysis section, timely mute is allowed to be performed immediately after the change in the emphasis information.

In the case where the automatic mute processing section performs automatic mute based on a change in channel mode information obtained by the header analysis section, timely mute is allowed to be performed immediately after the change in the channel mode information.

In the case where the automatic mute processing section performs automatic mute based on a change in layer information obtained by the header analysis section, timely mute is allowed to be performed immediately after the change in the layer information.

In the case where the automatic mute processing section performs automatic mute based on a change in ID information obtained by the header analysis section, timely mute is allowed to be performed immediately after the change in the ID information.

The decoding circuit according to the present invention includes an automatic mute timer setting section in which an automatic mute time duration can be set by the CPU. The automatic mute processing section can execute automatic mute for a duration of time, which is set by the automatic mute timer setting section based on a change in at least one decoding parameter obtained by the header analysis section. Thus, the automatic mute is allowed to be performed for the duration of time set by the automatic mute timer setting section immediately after the change in the decoding parameter.

The decoding circuit according to the present invention includes an automatic mute release instruction section which can be set by the CPU to instruct automatic mute release. The automatic mute processing section can execute automatic mute, based on a change in at least one decoding parameter obtained by the header analysis section, until being instructed to release the automatic mute by the automatic mute release instruction section. Thus, the timely start of the automatic mute is realized immediately after the change in the decoding parameter and the mute is allowed to be performed until the automatic mute release instruction section issues an instruction to release the automatic mute upon receipt of an instruction from the CPU.

The present invention also provides a reproduction apparatus including the above-described decoding circuit. The reproduction apparatus according to the present invention reproduces an audio signal obtained as a result of decoding processing performed on an encoded bit stream, without an extraneous or discordant sound even when any of the decoding parameters is changed.

As described above, the present invention provides a decoding circuit for decoding an encoded bit stream without outputting an extraneous or discordant sound even when a decoding parameter changes during reproduction, and a reproduction apparatus including such a decoding circuit.

Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be broadly construed. 

What is claimed is:
 1. A decoding circuit for receiving a bit stream including an encoded audio signal and header information used for decoding the encoded audio signal, and decoding the encoded audio signal based on the header information, the decoding circuit comprising: a header analysis section for outputting at least one decoding parameter obtained from the header information and decoding parameter change information indicating whether or not the at least one decoding parameter has been changed; a signal processing section for decoding the encoded audio signal, based on the at least one decoding parameter, into a decoded signal and outputting the decoded signal; an automatic mute processing section for executing automatic mute on the decoded signal after the at least one decoding parameter is changed; and an output section for outputting the decoded signal output from the automatic mute processing section.
 2. A decoding circuit according to claim 1, wherein the automatic mute processing section executes the automatic mute for a prescribed duration of time.
 3. A decoding circuit according to claim 1, further comprising a host interface section for communicating with a control circuit for controlling the decoding circuit.
 4. A decoding circuit according to claim 3, wherein the host interface section includes an automatic mute instruction section which is set to instruct whether or not automatic mute is necessary.
 5. A decoding circuit according to claim 4, wherein: the at least one decoding parameter includes sampling frequency information, the decoding parameter change information is sampling frequency change information indicating whether or not the sampling frequency information has been changed, the automatic mute processing section executes the automatic mute based on the sampling frequency change information, and the automatic mute processing instruction section includes a sampling frequency change automatic mute instruction section which is set to instruct whether or not the automatic mute is necessary based on the change in the sampling frequency information.
 6. A decoding circuit according to claim 4, wherein: the at least one decoding parameter includes emphasis information, the decoding parameter change information is emphasis change information indicating whether or not the emphasis information has been changed, the automatic mute processing section executes the automatic mute based on the emphasis change information, and the automatic mute processing instruction section includes an emphasis change automatic mute instruction section which is set to instruct whether or not the automatic mute is necessary based on the change in the emphasis information.
 7. A decoding circuit according to claim 4, wherein: the at least one decoding parameter includes channel mode information, the decoding parameter change information is channel mode change information indicating whether or not the channel mode information has been changed, the automatic mute processing section executes the automatic mute based on the channel mode change information, and the automatic mute processing instruction section includes a channel mode change automatic mute instruction section which is set to instruct whether or not the automatic mute is necessary based on the change in the channel mode information.
 8. A decoding circuit according to claim 4, wherein the bit stream includes an MPEG encoded audio bit stream.
 9. A decoding circuit according to claim 8, wherein: the at least one decoding parameter includes layer information, the decoding parameter change information is layer change information indicating whether or not the layer information has been changed, the automatic mute processing section executes the automatic mute based on the layer change information, and the automatic mute processing instruction section includes a layer change automatic mute instruction section which is set to instruct whether or not the automatic mute is necessary based on the change in the layer information.
 10. A decoding circuit according to claim 8, wherein: the at least one decoding parameter includes ID information, the decoding parameter change information is ID change information indicating whether or not the ID information has been changed, the automatic mute processing section executes the automatic mute based on the ID change information, and the automatic mute processing instruction section includes an ID change automatic mute instruction section which is set to instruct whether or not the automatic mute is necessary based on the change in the ID information.
 11. A decoding circuit according to claim 3, further comprising an initialization section for automatically initializing decoding processing performed by the decoding circuit, wherein the host interface section includes an initialization instruction section for instructing the initialization section to initialize the decoding processing upon receipt of an instruction from the control circuit.
 12. A decoding circuit according to claim 3, wherein the host interface section includes: a parameter display section for outputting the at least one decoding parameter to the control circuit, and a parameter change interrupt section for outputting the decoding parameter change information to the control circuit.
 13. A decoding circuit according to claim 3, wherein: the host interface section includes an automatic mute timer setting section for setting a time duration, and the automatic mute processing section terminates the automatic mute based on an instruction from the automatic mute timer setting section.
 14. A decoding circuit according to claim 3, wherein: the host interface section includes an automatic mute release instruction section which is set by the control circuit whether or not to instruct automatic mute release, the automatic mute processing section terminates the automatic mute based on an instruction from the automatic mute release instruction section.
 15. A decoding circuit according to claim 1, wherein: the at least one decoding parameter includes sampling frequency information, the decoding parameter change information is sampling frequency change information indicating whether or not the sampling frequency information has been changed, and the automatic mute processing section starts the automatic mute based on the sampling frequency change information.
 16. A decoding circuit according to claim 1, wherein: the at least one decoding parameter includes emphasis information, the decoding parameter change information is emphasis change information indicating whether or not the emphases information has been changed, and the automatic mute processing section starts the automatic mute based on the emphasis change information.
 17. A decoding circuit according to claim 1, wherein: the at least one decoding parameter includes channel mode information, the decoding parameter change information is channel mode change information indicating whether or not the channel mode information has been changed, and the automatic mute processing section starts the automatic mute based on the channel mode change information.
 18. A decoding circuit according to claim 1, wherein the bit stream includes an MPEG encoded audio bit stream.
 19. A decoding circuit according to claim 18, wherein: the at least one decoding parameter includes layer information, the decoding parameter change information is layer change information indicating whether or not the layer information has been changed, and the automatic mute processing section starts the automatic mute based on the layer change information.
 20. A decoding circuit according to claim 18, wherein: the decoding parameter includes ID information, the decoding parameter change information is ID change information indicating whether or not the ID information has been changed, and the automatic mute processing section starts the automatic mute based on the ID change information.
 21. A reproduction apparatus, comprising: a decoding circuit according to claim 1; and a control circuit for controlling the decoding circuit.
 22. A reproduction apparatus according to claim 21, further comprising a medium data extraction circuit for extracting an encoded audio signal and header information from an input encoded audio bit stream and outputting the encoded audio signal and the header information to the decoding circuit.
 23. A reproduction apparatus according to claim 22, further comprising a D/A converter for D/A converting a decoded signal output from the decoding circuit.
 24. A reproduction apparatus according to claim 23, wherein the control circuit stops an operation of the medium data extraction circuit based on decoding parameter change information obtained from the header information.
 25. A reproduction apparatus according to claim 23, wherein the control circuit sets a sampling frequency for the D/A converter based on the decoding parameter change information obtained from the header information.
 26. A reproduction apparatus according to claim 23, wherein the control circuit resets the decoding circuit based on the decoding parameter change information obtained from the header information.
 27. A reproduction apparatus according to claim 23, wherein the control circuit restarts an operation of the medium data extraction circuit based on the decoding parameter change information obtained from the header information.
 28. A decoding circuit according to claim 1, wherein the automatic mute processing section can perform fade-out processing immediately before the automatic mute on the decoded signal or fade-in processing at the restart immediately after the automatic mute on the decoded signal. 